Cluster tool systems and methods for processing wafers

ABSTRACT

The present invention provides exemplary cluster tool systems and methods for processing wafers, such as semiconductor wafers. One method includes providing a wafer having initial thickness variations between two wafer surfaces. The wafer is processed (Step  216 ) through a first module ( 300 ), with the first module having apparatus for performing a grinding process, a clean process and a metrology process, all preferably within a clean room environment ( 310 ). Wafer processing through the first module includes performing the grinding process, clean process and metrology process. The method further includes defining an edge profile on the wafer and processing (Step  222 ) the wafer through a second module ( 400 ).

CROSS-REFERENCES TO RELATED APPLICATIONS

[0001] This application claims the benefit of the following U.S.Provisional Applications, the complete disclosures of which areincorporated herein by reference:

[0002] Provisional application Ser. No. 60/190,278 (Attorney Docket No.20648-000100), filed on Mar. 17, 2000;

[0003] Provisional application Ser. No. 60/190,221 (Attorney Docket No.20468-000300), filed on Mar. 17, 2000; and

[0004] Provisional application Ser. No. 60/202,495 (Attorney Docket No.20468-001000) filed on May 5, 2000.

BACKGROUND OF THE INVENTION

[0005] The present invention is directed to the processing of wafers,substrates or disks, such as silicon wafers, and more specifically tocluster tool systems and methods for processing wafers prior to deviceformation.

[0006] Wafers or substrates with exemplary characteristics must first beformed prior to the formation of circuit devices. In determining thequality of the semiconductor wafer, the flatness of the wafer is acritical parameter to customers since wafer flatness has a direct impacton the subsequent use and quality of semiconductor chips diced from thewafer. Hence, it is desirable to produce wafers having as near a planarsurface as possible.

[0007] In a current practice, cylindrical boules of single-crystalsilicon are formed, such as by Czochralski (CZ) growth process. Theboules typically range from 100 to 300 millimeters in diameter. Theseboules are cut with an internal diameter (ID) saw or a wire saw intodisc-shaped wafers approximately one millimeter (mm) thick. The wire sawreduces the kerf loss and permits many wafers to be cut simultaneously.However, the use of these saws results in undesirable waviness of thesurfaces of the wafer. For example, the topography of the front surfaceof a wafer may vary by as much as 1-2 microns (μ) as a result of thenatural distortions or warpage of the wafer as well as the variations inthe thickness of the wafer across its surface. It is not unusual for theamplitude of the waves in each surface of a wafer to exceed fifteen (15)micrometers. The surfaces need to be made more planar (planarized)before they can be polished, coated or subjected to other processes.

[0008]FIG. 1 depicts a typical prior art method 10 for processing asilicon wafer prior to device formation. Method 10 includes a slice step12 as previously described to remove a disc-shaped portion of wafer fromthe silicon boule. Once the wafer has been sliced, the wafer is cleanedand inspected (Step 14). Thereafter, an edge profile process (Step 16)is performed. Once the edge profile has been performed, the wafer isagain cleaned and inspected (Step 18), and is laser marked (Step 20).

[0009] Next, a lapping process (Step 22) is performed to controlthickness and remove bow and warp of the silicon wafer. The wafer issimultaneously lapped on both sides with an abrasive slurry in a lappingmachine. The lapping process may involve one or more lapping steps withincreasingly finer polishing grit. The wafer is then cleaned (Step 24)and etched (Step 26) to remove damage caused by the lapping process. Theetching process may involve placing the wafer in an acid bath to removethe outer surface layer of the wafer. Typically, the etchant is amaterial requiring special handling and disposal. Thereafter, anadditional cleaning of the wafer (Step 28) is performed.

[0010] The prior art method continues with a donor anneal (Step 30)followed by wafer inspection (Step 32). Thereafter, the wafer edge ispolished (Step 24) and the wafer is again cleaned (Step 36). Typicalwafer processing involves the parallel processing of a multitude ofwafers. Hence at this juncture wafers may be sorted, such as bythickness (Step 38), after which a double side polish process isperformed (Step 40).

[0011] The wafers then are cleaned (Step 42) and a final polish (Step44) is performed. The wafers are again cleaned (Step 46), inspected(Step 48) and potentially cleaned and inspected again (Steps 50 and 52).For epitaxial substrates, a poly or oxide layer is overlaid to seal inthe dopants after inspection Step 52. At this point, the wafer is packed(Step 54), shipped (Step 56) and delivered to the end user (Step 58).Hence, as seen in FIG. 1 and as described above, typical waferprocessing involves a lengthy, time consuming process with a largenumber of processing steps.

[0012] A number of deficiencies exist with the prior art method. As canbe seen from even a precursory review of FIG. 1, the prior art methodrequires a large number of steps to transform a wafer slice into asubstrate suitable for creating circuit devices. The large number ofprocess steps involved negatively effects production throughput,requires a large production area, and results in high fabrication costs.Additionally, each of the steps in FIG. 1 are typically performed atindividual process stations. The stations are not grouped or clusteredtogether, and manual delivery of the wafers between stations is oftenused.

[0013] In addition to the large number of process steps, at least someof the prior art steps themselves are slow or produce unacceptableresults. For example, compared to a grinding process, the lappingprocess is slow and must be followed by careful cleaning and etchingsteps to relieve stresses before the wafer is polished. These additionalsteps cause the conventional method to be more expensive andtime-consuming than methods of the present invention. Also, the etchingprocess employed after the lapping step is undesirable from anenvironmental standpoint, because the large amount of strong acids usedmust be disposed of in an acceptable way.

[0014] In another prior art method, a grinding process replaces thelapping procedure in FIG. 1. A first surface of the wafer is drawn orpushed against a hard flat holder while the second surface of the waferis ground flat. The forces used to hold the wafer elastically deform thewafer during grinding of the second surface. When the wafer is released,elastic restoring forces in the wafer cause it to resume its originalshape, and it can be seen that the waves in the first surface have beentransferred to the surface that has been ground. Thus while thistechnique produces a wafer of more uniform thickness, it does noteliminate the residual saw waves.

[0015] One technique used to try to solve the residual wave problem isto apply a thick coating of grease or wax to the wafer holder and thenbring one side of the wafer into contact with the exposed surface of thegrease. The wafer is then partially supported by the grease, and becausethe weight of the wafer is distributed uniformly across the wafer, thewafer is not deformed from its original shape. At this point, thetemperature could be lowered so that the grease would become thicker soas to better oppose any localized stresses that might be imposed on thewafer by the grinding process. In place of grease, a wax or pitch couldbe used.

[0016] This technique is undesirable, however, because the grease clogsthe pores in the vacuum plate holding the wafer. Another disadvantage isthe need to remove the grease or other material from the wafer after thegrinding has been completed. This can be difficult due to the stickinessor tackiness of the wax, grease or other materials. The wafer, vacuumplate and/or the cleaning device often has residual material sticking toit. For these and other reasons, the above technique is undesirable.

[0017] Additional deficiencies in the current art, and improvements inthe present invention, are described below and will be recognized bythose skilled in the art.

SUMMARY OF THE INVENTION

[0018] The present invention provides exemplary cluster tool systems andmethods for processing wafers, such as semiconductor wafers. One methodof the present invention includes providing a wafer having initialthickness variations between two wafer surfaces. The wafer is processedthrough a first module, with the first module having apparatus forperforming a grinding process, a clean process and a metrology process.Wafer processing through the first module includes performing thegrinding process, clean process and metrology process. The methodfurther includes defining an edge profile on the wafer and processingthe wafer through a second module. The wafer edge profile preferably isperformed after first module processing, though need not be.

[0019] The second module includes apparatus for performing a double sidepolish (DSP) process, a clean process and a metrology process. Again,processing the wafer through the second module includes the above notedprocesses. In this manner, the wafer processing is compartmentalized inan efficient manner which results in the reduction of process stepscompared to the prior art. Further, in one embodiment, the wafer edgeprofile is defined subsequent to the grinding process. In this manner,the edge profiling helps remove damage to the wafer edge caused by thegrinding process.

[0020] In one aspect, the first and second modules each comprise acluster tool defining a clean room or other micro environment.

[0021] In one embodiment of the present invention, the first moduleprocessing further includes an etch process which reduces the waferthickness by less than about ten (10) microns. One advantage of thepresent invention is the use of the grinding process to provide agenerally flat wafer surface, In such a process, a reduced amount ofetching is required to produce a flat surface and remove grinding damagefrom the wafer.

[0022] In an aspect of the present invention, the first module metrologyprocess occurs simultaneously with the grinding process. In a furtheraspect, the first module metrology process produces a metrology profilefor the wafer. Processing the wafer through the first module furtherincludes modifying the grinding process in response to the wafermetrology profile. Alternatively, the first module metrology processoccurs after the wafer grinding process.

[0023] In one aspect, the wafer edge is polished after the wafer edgeprofile has been defined. In another aspect, the method includesprocessing the wafer through a third module. The third module includesapparatus for performing, and the method includes performing, a finishpolish process, a clean process and a metrology process.

[0024] The compact nature of the cluster tools according to the presentinvention facilitate their use within a fabrication facility. In oneaspect of the invention, after completion of processing through thethird module, the processed wafer is directly provided to a processchamber for fabrication of a semiconductor device. In this manner,packing, shipping and delivery steps as shown in FIG. 1 are avoided.Alternatively, methods of the present invention may be performed offsitefrom the fabrication facility, with wafers intended to be processedtherethrough first being packaged, shipped and delivered to thefabrication facility.

[0025] In one aspect of the invention, the wafer has a total thicknessvariation (TTV) between two surfaces of less than about 0.3 micronsafter processing through the second module. In another aspect, the waferhas a side flatness quotient reading (SFQR) of less than 0.12 micronsafter processing through the second module. In still another aspect, theTTV between the two wafers surfaces is less than about 0.5 microns, isless than about 0.3 microns, or is less than about 0.2 microns afterprocessing through a finish polishing module.

[0026] In alternative aspects, the methods of processing a wafer furtherinclude laser marking the wafer prior to defining the edge profile,and/or performing a donor anneal process prior to defining the edgeprofile. In one aspect of the present invention, the wafer is processedthrough a third module comprising apparatus for performing an edgeprofile process and an edge polishing process.

[0027] The method further includes exemplary wafer processing systemsaccording to the present invention. In one aspect of the presentinvention, the wafer processing system includes means for grinding thewafer, means for cleaning the wafer, and means for testing the wafermetrology, wherein the means for grinding, cleaning and testing arecontained within a single clean room environment. In one embodiment, thesystem includes a first clean room environment containing a grinder forgrinding first and second wafer surfaces, an etcher for etching thewafer, a cleaner for cleaning the wafer, and a metrology tester fortesting wafer metrology. In one aspect, the etcher and cleaner comprisethe same device.

[0028] In one aspect, the system further includes a transfer mechanism,such as a robot, adapted to transfer the wafer between the grinder andthe etcher within the first clean room environment. In another aspect,the system includes a second clean room environment comprising an edgegrinder for defining an edge profile of the wafer and an edge polisherfor polishing the wafer edge. In alternative aspects, the systemincludes a third clean room containing a polisher, a cleaner and ametrology tester, and/or a fourth clean room comprising a finishpolisher, a cleaner and a metrology tester.

[0029] Other objects, features and advantages of the present inventionwill become more fully apparent from the following detailed description,the appended claims and the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0030]FIG. 1 depicts a prior art method for processing a silicon wafer;

[0031]FIG. 2 is a simplified flow diagram of a wafer processing methodaccording to the present invention;

[0032] FIGS. 3A-C depict grind damage cluster tools according to thepresent invention;

[0033]FIG. 4 depicts an edge profile/polish cluster tool according tothe present invention;

[0034]FIGS. 5A and 5B depict double side polish cluster tools accordingto the present invention; and

[0035]FIG. 6 depicts a finish polish cluster tool according to thepresent invention.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

[0036]FIG. 2 depicts an exemplary method 200 of the present invention.Method 200 includes a slice process 210, using a wire saw, innerdiameter saw or the like, to create a generally disc-shaped wafer orsubstrate. In one embodiment, the wafer is a silicon wafer.Alternatively, the wafer may comprise polysilicon, germanium, glass,quartz, or other materials. Further, the wafer may have an initialdiameter of about 200 mm, about 300 mm, or other sizes, includingdiameters larger than 300 mm.

[0037] The wafer is cleaned and inspected (Step 212) and then may, ormay not, be laser-marked (Step 214). Laser marking involves creating analphanumeric identification mark on the wafer. The ID mark may identifythe wafer manufacturer, flatness, conductivity type, wafer number andthe like. The laser marking preferably is performed to a sufficientdepth so that the ID mark remains even after portions of the wafer havebeen removed by subsequent process steps such as grinding, etching,polishing, and the like.

[0038] Thereafter, the wafer is processed through a first module (Step216), with details of embodiments of the first module described below inconjunction with FIGS. 3A-3C. First module processing (Step 216)includes a grinding process, an etching process, a cleaning process andmetrology testing of the wafer. In this module, the use of a grindingprocess in lieu of lapping helps to remove wafer bow and warpage. Thegrinding process of the present invention also is beneficial in removingwafer surface waves caused by the wafer slicing in Step 210. Benefits ofgrinding in lieu of lapping include reduced kerf loss, better thicknesstolerance, improved wafer shape for polishing and better laser mark dotdepth tolerance, and reduced damage, among others.

[0039] The etching process within the first module is a more benignprocess than the prior art etch step described in conjunction withFIG. 1. For example, typical prior art etching (Step 26 in FIG. 1) mayinvolve the bulk removal of forty (40) or more microns of waferthickness. In contrast, the etch process of the present inventionpreferably removes ten (10) microns or less from the wafer thickness. Inone embodiment, the first module etch process removes between about two(2) microns to about five (5) microns of wafer material per side, or atotal of about four (4) to about ten (10) microns. In anotherembodiment, the first module etch process removes between about three(3) microns and about four (4) microns of wafer material per side for atotal of about six (6) to about (8) microns.

[0040] After first module processing, the wafer is subjected to a donoranneal (Step 218) and thereafter inspected (Step 220). The donor annealremoves unstable oxygen impurities within the wafer. As a result, theoriginal wafer resistivity may be fixed. In an alternative embodiment,donor anneal is not performed.

[0041] The wafer then is processed through a second module (Step 222) inwhich an edge process is performed. The edge process includes both anedge profile and an edge polish procedure. Edge profiling may includeremoving chips from the wafer edge, controlling the diameter of thewafer and/or the creation of a beveled edge. Edge profiling also mayinvolve notching the wafer to create primary and secondary flat edges.The flats facilitate wafer alignment in subsequent processing stepsand/or provide desired wafer information (e.g., conductivity type). Inone embodiment, one or both flats are formed near the ID mark previouslycreated in the wafer surface. One advantage of the present inventioninvolves performing the edge profiling after wafer grinding. In thismanner, chips or other defects to the wafer edge, which may arise duringgrinding or lapping, are more likely to be removed. Prior art edgeprofiling occurs before lapping, and edge polishing subsequent to thelapping step may not sufficiently remove edge defects.

[0042] The wafer is then processed through a third module (Step 224). Athird module process includes a double side polish, a cleaning processand wafer metrology. Wafer polishing is designed to remove stress withinthe wafer and smooth any remaining roughness. The polishing also helpseliminate haze and light point defects (LPD) within the wafer, andproduces a flatter, smoother finish wafer. As shown by the arrow in FIG.2, wafer metrology may be used to adjust the double side polishingprocess within the third module. In other words, wafer metrology may befeed back to the double side polisher and used to adjust the DSP devicein the event the processed wafer needs to have different or improvedcharacteristics, such as flatness, or to further polish out scratches.

[0043] Thereafter, the wafer is subjected to a finish polish, a cleaningprocess and metrology testing, all within a fourth process module (226).The wafer is cleaned (Step 228), inspected (Step 230) and delivered(Step 232).

[0044] The reduced number of clean and inspection steps, particularlynear the end of the process flow, are due in part to the exemplarymetrology processing of the wafer during prior process steps. Wafermetrology testing may test a number of wafer characteristics, includingwafer flatness, haze, LPD, scratches and the like. Wafer flatness may bedetermined by a number of measuring methods known to those skilled inthe art. For example, “taper” is a measurement of the lack ofparallelism between the unpolished back surface and a selected focalplane of the wafer. Site Total Indicated Reading (STIR) is thedifference between the highest point above the selected focal plane andthe lowest point below the focal plane for a selected portion (e.g., 1square cm) of the wafer, and is always a positive number. Site FocalPlane Deviation (SFPD) is the highest point above, or the lowest pointbelow, the chosen focal plane for a selected portion (e.g., 1 square cm)of the wafer and may be a positive or negative number. Total thicknessvariation (TTV) is the difference between the highest and lowestelevation of the polished front surface of the wafer.

[0045] Further, metrology information, in one embodiment, is fed backand used to modify process parameters. For example, in one embodimentmetrology testing in the first module occurs after wafer grinding andmay be used to modify the grinding process for subsequent wafers. In oneembodiment, wafers are processed through the first module in series.More specifically, each station within the first module processes asingle wafer at a time. In this manner, metrology information may be fedback to improve the grinding or other process after only about one (1)to five (5) wafers have been processed. As a result, a potential problemcan be corrected before a larger number of wafers have been processedthrough the problem area, thus lowering costs.

[0046] Further, the present invention produces standard process timesfor each wafer. More specifically, each wafer is subjected toapproximately the same duration of grinding, cleaning, etching, etc. Thedelay between each process also is the same or nearly the same for eachwafer. As a result, it is easy to troubleshoot within the presentinvention methods and systems.

[0047] In contrast, prior art methods typically uses a batch processmode for a number of process steps. For example, a batch containing alarge number of wafers (say, twenty (20)) may be lapped one to a few ata time (say, one (1) to four (4) at a time). After all twenty have beenlapped, the batch of twenty wafers then are cleaned together as a group(Step 24), and etched together as a group (Step 26). As a result, thewafers that were lapped first sit around for a longer period of timeprior to cleaning than do the wafers lapped last. This varying delayeffects wafer quality, due in part to the formation of a greater amountof haze, light point defects, and other time-dependent wafer defects.One negative outcome of irregular process times is the resultantdifficulty in locating potential problems within the process system.

[0048] As with the first module, metrology information may be fed backwithin the second, third and fourth modules. For example, metrologyinformation may be fed back to the double side polisher or finishpolisher to adjust those processes to produce improved results.Additionally, in one embodiment, metrology information is fed backwithin the third and/or fourth module in real time. As a result, processsteps such as the double side polishing can be modified duringprocessing of the same wafer on which metrology testing has occurred.

[0049] With reference to FIGS. 3-6, additional details on processmodules according to the present invention will be provided. It will beappreciated by those skilled in the art that the process modulesdescribed in FIGS. 3-6 are embodiments of the present invention, fromwhich a large number of variations for each module exist within thescope of the present invention. Further, additional process steps may beremoved or added, and process steps may be rearranged within the scopeof the present invention.

[0050]FIG. 3A depicts a grind damage cluster module described as firstmodule 216 in conjunction with FIG. 2. First module 300 defines a cleanroom environment 310 in which a series of process steps are carried out.Wafers that have been processed through Step 214 (FIG. 2) are receivedin first module 300 via a portal, such as a front opening unified pod(FOUP) 312. First module 300 is shown with two FOUPs 312, although alarger or smaller number of FOUPs/portals may be used. FOUPs 312 areadapted to hold a number of wafers so that the frequency of ingress intothe clean room environment 310 may be minimized. A transfer device 314,schematically depicted as a robot, operates to remove a wafer from FOUPs312 and place the wafer on a grinder 318. If needed, transfer device 314travels down a track 316 to properly align itself, and hence the wafer,in front of grinder 318. Grinder 318 operates to grind a first side ofthe wafer.

[0051] The wafer may be held down on grinder 318 by way of a vacuumchuck, and other methods. Once grinder 318 has ground the first side ofthe wafer, the wafer is cleaned in cleaner 322 and the transfer device314 transfers the wafer back to grinder 318 for grinding the converseside of the wafer. In one embodiment, wafer grinding of both wafer sidesremoves about forty (40) microns to about seventy (70) microns of waferthickness. After the second wafer side is ground, the wafer is againcleaned in cleaner 322. In one embodiment, cleaning steps occur ongrinder 318 subsequent to grinding thereon. In one embodiment, cleaningand drying are accomplished by spraying a cleaning solution on the waferheld by or near the edges and spun.

[0052] In another embodiment, at least one side of the wafer issubjected to two sequential grinding steps on grinder 318. The twogrinding processes preferably include a coarse grind followed by a finegrind. Grinder 318 may include, for example, two different grindingplatens or pads with different grit patterns or surface roughness. Inone embodiment, the wafer is cleaned on grinder 318 between the twogrinding steps to the same wafer side. Alternatively, cleaning may occurafter both grinding steps to the same wafer side.

[0053] In some embodiments, transfer device 314 transfers the wafer fromcleaner 322 to a backside polisher 326. For example, this process flowmay occur for 200 mm wafers. In this embodiment, the back side ispolished and not ground, or both ground and polished.

[0054] As shown in FIG. 3A, a second grinder 320 and a second cleaner324 are provided within module 300. In this manner, two wafers may besimultaneously processed therethrough. Since both grinders 318, 320 havea corresponding cleaner 322, 324, wafer processing times are consistenteven if two wafers are being ground simultaneously on grinders 318, 320.In one embodiment, grinders 318 and 320 are used to grind opposite sidesof the same wafer. In this case, one side of the wafer is ground ongrinder 318 and the other side of the same wafer is ground on grinder320. As with grinder 318, wafers may be ground on grinder 320 and thencleaned on grinder 320 before removal, or cleaned in cleaner 324.

[0055] Once the wafers have been ground, a second transfer device 336,again a robot in one embodiment, operates to transfer the wafer to anetcher 330. Etcher 330 operates to remove material from the wafer,preferably a portion on both primary sides of the wafer. The etchingprocess is designed to remove stresses within the silicon crystal causedby the grinding process. Such an operation, in one embodiment, removesten (10) microns or less of total wafer thickness. In this manner,etcher 330 operates to remove less wafer material than in prior art etchprocesses. Further, the present invention requires less etchantsolution, and hence poses fewer environmental problems related todisposal of the acids or other etchants.

[0056] Wafer metrology is then tested at a metrology station 328. In oneembodiment wafer metrology is tested subsequent to grinding on grinder318, and prior to the etching within etcher 330. Alternatively, wafermetrology is tested subsequent to etching in etcher 330. In stillanother embodiment, wafer metrology is tested both prior to andsubsequent to the etching process. Evaluation of wafer metrologyinvolves the testing of wafer flatness and other wafer characteristicsto ensure the wafer conforms to the desired specifications. If the waferdoes not meet specifications, the wafer is placed in a recycle area 342,which in one embodiment comprises a FOUP 342 (not shown in FIG. 3A).Wafers with acceptable specifications are placed in an out portal orFOUP 340 for removal from first module 300.

[0057] As shown and described in conjunction with FIG. 3A, first module300 provides an enclosed clean room environment in which a series ofprocess steps are performed. Wafers are processed in series throughfirst module 300. Hence, each wafer has generally uniform or uniformprocess time through the module as well as generally uniform or uniformdelay times between process steps. Further, by immediately cleaning andetching the wafer after grinding, the formation of haze and light pointdefects (LPD) within the wafer are reduced. Such a module configurationis an improvement over the prior art in which wafers are typicallyprocessed during the lapping step in batch mode. As a result, somewafers will wait longer before the cleaning or etching steps than otherswithin the same batch. As a result, haze and other wafer defects varyfrom wafer to wafer, even between wafers within the same batch. Such ashortcoming of the prior art can make it difficult if not impossible toisolate problems within the wafer process flow in the event defectivewafers are discovered.

[0058] An additional benefit of first module 300 is its compact size. Inone embodiment, module 300 has a width 342 that is about 9 feet 3 inchesand a length 344 that is about 12 feet 6 inches. In another embodiment,first module 300 has a footprint ranging between about ninety (90)square feet (sqft) and about one hundred and fifty (150) square feet. Itwill be appreciated by those skilled in the art that the width andlength, and hence the footprint of first module 300, may vary within thescope of the present invention. For example, additional grinders 318,320 may be added within first module 300 to increase the footprint ofmodule 300. In one embodiment, first module 300 is adapted to processabout thirty (30) wafers per hour. In another embodiment, first module300 is adapted to process between about twenty-nine (29) and aboutthirty-three (33) 300 mm wafers per hour.

[0059]FIG. 3B depicts an alternative embodiment of a grind damagecluster module according to the present invention. Again, the grinddamage cluster module 350 may correspond to first module 216 describedin conjunction with FIG. 2. Module 350 includes many of the samecomponents as the embodiment depicted in FIG. 3A, and like referencenumerals are used to identify like components. Module 350 receiveswafers or substrates to be processed at portal 312, identified as a sendFOUP 312 in FIG. 3B. Wafers are transferred by transfer device 314,shown as wet robot 314, to a preprocessing station 354. In oneembodiment, transfer device 314 travels on a track, groove, raisedmember or other mechanism which allows transfer device 314 to reachseveral process stations within module 350.

[0060] At preprocessing station 354, a coating is applied to one side ofthe wafer. In one embodiment, a polymer coating is spun on the wafer toprovide exemplary coverage. This coating then is cured using ultraviolet(UV) light to provide a low shrink, rapid cured coating on one side ofthe wafer. In addition to UV curing, curing of the coating may beaccomplished by heating and the like. In a particular embodiment, thecoating is applied to a thickness between about five (5) microns andabout thirty (30) microns.

[0061] Once cured, the coating provides a completely or substantiallytack free, stress free surface on one side of the wafer. In oneembodiment of the present invention, transfer device 314 transfers thewafer to grinder 318, placing the polymer-coated side down on thegrinder 318 platen. In one embodiment, the platen is a porous ceramicchuck which uses a vacuum to hold the wafer in place during grinding.The waves created during wafer slicing are absorbed by the coating andnot reflected to the front side of the wafer when held down during thegrinding process. After the first wafer side is ground on grinder 318,the wafer is flipped over and the second side is ground. As described inconjunction with FIG. 3A, an in situ clean of the wafer may occur beforeturning the wafer, or the wafer may be cleaned subsequent to grinding ofboth sides. Again, the second side grinding may occur on grinder 318 orgrinder 320. Grinding of the second side removes the cured polymer, anda portion of the second wafer surface resulting in a generally smoothwafer on both sides, with little to no residual surface waves.Additional details on exemplary grinding methods are discussed in U.S.patent application Ser. No. ______(Attorney Docket No. 20468-001010),filed contemporaneously herewith, the complete disclosure of which isincorporated herein by reference.

[0062] After grinding on grinder 318 and/or 320, the wafer istransferred to a combined etch/clean station 352 for wafer etch. Again,wafer etching in station 352 removes a smaller amount of wafer material,and hence requires a smaller amount of etchant solutions, than istypically required by prior art processes.

[0063] Processing continues through module 350 ostensibly as describedin FIG. 3A. The wafer metrology is tested at metrology station 328.Wafers having desired characteristics are transferred by transfer device336, shown as a dry robot, to out portals 340, identified as receiveFOUPS 340 in FIG. 3B. Wafers having some shortcoming or undesirableparameter are placed in a recycle area 342, shown as a buffer FOUP 342,for appropriate disposal.

[0064] In one embodiment, module 350 has a width 342 at its widest pointof about one hundred and fourteen (114) inches, and a length at itslongest point of about one hundred and forty-five inches (145), with atotal footprint of about one hundred and fourteen square feet (114sqft). As will be appreciated by those skilled in the art, thedimensions and footprint of module 350 may vary within the scope of thepresent invention.

[0065] Still another embodiment of a grind damage cluster moduleaccording to the present invention is shown in FIG. 3C. FIG. 3C depictsa first module 360 having similar stations and components as module 350described in FIG. 3B. However, module 350 is a flow through module, withwafers being received at one end or side of module 350 and exiting anopposite end or side of module 350. Module 360 has FOUPS 312, 342 and340 grouped together. Such a configuration provides a single entry pointinto module 360, and hence into clean room environment 310. Transferdevices 314 and 336 again facilitate the movement of wafers from stationto station within module 360. As shown in FIGS. 3B and 3C, transferdevice 314 travels on mechanism 316, as discussed in conjunction withFIG. 3B. Transfer device 336 operates from a generally fixed positionwith arms or platens extending therefrom to translate the wafer to thedesired processing station. Module 360 further includes station 354 forapplication of a wafer coating, such as the UV cured polymer coatingdescribed above.

[0066] Turning now to FIG. 4, an exemplary second module comprising anedge profile and edge polishing module will be described. Second module400 again includes a clean room environment 410 to facilitate cleanoperations. Second module 400 has a portal 412 for receiving wafers tobe processed. Again, in one embodiment, portal 412 is one or more FOUPs.A robot or other transfer device 414 operates to take a wafer fromportal 412 and transfer the wafer to an edge profiler/polisher 418. Edgeprofiler/polisher 418 may comprise one device, or two separate deviceswith the first device for profiling and the second device for polishing.Transfer device 414 may travel down a track 416 to permit properplacement of the wafer in the edge profiler/polisher 418.

[0067] The edge of the wafer is profiled and polished as described inconjunction with FIG. 2. In one embodiment, edge profiling removes aboutten (10) microns to about fifty (50) microns of material from thediameter of the wafer, with a resultant diameter tolerance of about+/−0.5 μ. After edge profiling and polishing, a transfer device 420operates to transfer the wafer to a cleaner 430. Again, transfer device420 may travel on a track 422 to place the wafer in cleaner 430. Cleaner430 may comprise a mixture of dilute ammonia, peroxide, and water, or anammonia peroxide solution and soap, followed by an aqueous clean, andthe like.

[0068] Subsequent to cleaning in cleaner 430, the wafer is transferredto a metrology station 432 at which wafer metrology is examined. Anout-portal 434 is positioned to receive wafers having successfullycompleted processing through second module 400. In one embodiment,portal 434 is a FOUP which collects wafers meeting desiredspecifications.

[0069] Again, rejected wafers are set aside in a separate area or FOUP.

[0070] Second module 400 has a compact configuration similar to firstmodule. In one embodiment, second module 400 has a width 450 of about 7feet 6 inches and a length 460 of about 22 feet 11 inches. In anotherembodiment, second module 400 has a footprint ranging between aboutninety (90) square feet (sqft) and about one hundred and fifty (150)square feet. The module 400 shown in FIG. 4 may be used to carry outprocess step 222 depicted in FIG. 2. In one embodiment, second module400 processes about thirty (30) wafers per hour. In another embodiment,second module 400 is adapted to process between about twenty-nine (29)and about thirty-three (33) 300 mm wafers per hour. In still anotherembodiment, second module 400 processing occurs prior to first module300 processing. In this manner, edge profile and/or edge polishprocedures occur before wafer grinding.

[0071]FIG. 5A depicts a third module 500 comprising a double sidepolisher for use in process step 224 shown in FIG. 2. Module 500 againincludes an in-portal 512 which may be one or more FOUPs in oneembodiment. Wafers are received in portal 512 and transferred within aclean room environment 510 by a transfer device 514. Transfer device514, which in one embodiment is a robot, may travel along a track 516 todeliver the wafer to one or more double side polishers (DSP) 518.

[0072] As shown in FIG. 5A, double side polisher 518 accommodates threewafers 520 within each polisher. It will be appreciated by those skilledin the art that a greater or fewer number of wafers may besimultaneously polished within DSP 518. Prior art double side polishing(DSP) typically polishes a batch of ten or more wafers at a time in adouble side polisher. The polisher initially only contacts the two orthree thickest wafers due to their increased height within the DSPmachine. Only after the upper layers of the thickest wafers are removedby polishing, are additional wafers polished within the batch. As aresult, the batch mode polishing takes longer, and uses more polishingfluids and deionized water than in the present invention.

[0073] Hence in one preferred embodiment of the present invention, threewafers are polished simultaneously. Subsequent to polishing on polisher518, the wafers are transferred via a transfer device 536, traveling ontrack 538 to a buffer station 522. Thereafter, the wafers are buffed,cleaned and dried. Either prior to or after processing through station522, or both, wafers are tested at a metrology station 540. For wafersmeeting desired specifications, transfer device 536 transfers thosewafers to an out-portal 544, again, one or more FOUPs in one embodiment.Wafers which do not meet specifications are placed in a reject FOUP 542.

[0074] As with prior modules, the third module 500 has a compactfootprint. In one embodiment, module 500 has a width 546 that is about13 feet 11 inches and a length 548 that is about 15 feet 11 inches. Inanother embodiment, third module 500 has a footprint ranging betweenabout one hundred (100) square feet (sqft) and about one hundred andeighty (180) square feet. Third module 500 may have a differentfootprint within the scope of the present invention.

[0075] In one embodiment, DSP 518 removes about twelve (12) microns ofwafer thickness from both sides combined, at a rate of about 1.25 to 2.0microns per minute. DSP 518 operates on a twelve (12) minute cycle timeper load. Hence, in one embodiment, two DSPs 518 process about thirty(30) wafers per hour. In another embodiment, third module 500 is adaptedto process between about twenty-nine (29) and about thirty-three (33)300 mm wafers per hour. It will be appreciated by those skilled in theart that DSP 518 process times, third module 500 throughput, and otherparameters may vary within the scope of the present invention. Forexample, additional DSPs 518 may be added to increase module 500throughput. In one embodiment, wafer metrology tested at metrologystation 540 is fed back to DSPs 518 to adjust DSP 518 operation asneeded to produce desired wafer metrology.

[0076]FIG. 5B depicts an alternative embodiment of a third moduleaccording to the present invention. As shown in FIG. 5B, third module550 comprises a double side polisher for use in process step 224 shownin FIG. 2, as well as several other components shown in FIG. 5A. As aresult, like components are identified with like reference numerals.Module 550 includes a clean/dry station 552 for wafer cleaning anddrying subsequent to wafer polishing in polisher 518. Transfer devices514 and 536, shown as a wet robot and a dry robot, respectively, operateto transfer wafers within module 550. In one embodiment, transfer device514 travels on a track, groove, raised feature or the like to reachseveral processing stations and portals 512, while transfer device 536operates from a fixed base.

[0077] While module 500 in FIG. 5A is a flow through module, with wafersreceived by module 500 at one side and exiting from an opposite side,module 550 in FIG. 5B groups portals 512 and 544. Again, such a groupingof in and out portals facilitates access to module 550 from a singlepoint or side. In one embodiment, a buffer or reject FOUPS (not shown)also is grouped with portals 512 and 544. Alternatively, one or more ofportals 512 and 544 may operate as a reject FOUPS.

[0078] Third module 550, in one embodiment, has a compact footprint witha width 546 at the widest point of about one hundred and forty two (142)inches and a length at the longest point of about one hundred andfifty-five inches (155).

[0079] Turning now to FIG. 6, a fourth module 600, comprising a finishpolish cluster, will be described. Fourth module 600 in one embodimentwill be used for process step 226 shown in FIG. 2. As with the priormodules, fourth module 600 defines a clean room environment 610 whichhas ingress and egress through one or more portals or FOUPs. Forexample, an in-portal or FOUP 612 receives a plurality of wafers forfinish polishing. Wafers are removed from FOUP 612 and transferred by atransfer device 614 along a track 616 to a finish polisher 618. Whiletwo finish polishers 618 are depicted in FIG. 6, a larger or smallernumber of polishers 618 may be used within the scope of the presentinvention.

[0080] Wafers are finish polished for about five (5) to six (6) minuteswithin finish polisher 618 in an embodiment. Wafers that have undergonefinish polishing are transferred to a single wafer cleaner 630 by atransfer device 636. Again, transfer device 636 in one embodimentcomprises a robot that travels along a track 638. After wafer cleaningat cleaner station 630, wafer metrology is again tested at a metrologystation 640. In one embodiment, metrology processing within fourthmodule 600 uses a feedback loop to provide data to finish polishers 618as a result of wafer metrology testing. In one embodiment, the feedbackloop is of sufficiently short duration to permit adjustments to thefinish polisher process prior to the polishing of the next wafer afterthe wafer being tested. Wafers which do not meet specification areplaced in a reject FOUP or portal 642 for proper disposal. Wafersmeeting specifications will be placed in an out-portal or FOUP 644 forsubsequent processing, packaging and shipping.

[0081] Fourth module 600, in one embodiment, has a width 650 of about 14feet 0 inches and a length 660 of about 16 feet 0 inches. In anotherembodiment, fourth module 600 has a footprint ranging between about onehundred (100) square feet (sqft) and about one hundred and eighty (180)square feet. Again, as with all prior modules, the exact size may varywithin the scope of the present invention. In one embodiment, fourthmodule 600 processes about thirty (30) wafers per hour. In anotherembodiment, fourth module 600 is adapted to process between abouttwenty-nine (29) and about thirty-three (33) 300 mm wafers per hour.

[0082] In one embodiment, the four modules 300, 400, 500 and 600, ortheir alternative embodiments, and ancillary equipment take up about4,000 square feet or less of a production facility. This total footprintis much smaller than required for prior art equipment performing similarprocesses. As a result, apparatus, systems and methods of the presentinvention may be incorporated more readily in smaller facilities, or aspart of a device fabrication facility in which circuit devices areformed. In this manner, the time and cost of packing and shipping, aswell as unpacking and inspecting, are avoided. The costs of packing andshipping can, for example, save on the order of about two (2) percent ormore of the total wafer processing costs. Additional details onexemplary in-fab wafer processing methods are discussed in U.S. patentapplication Ser. No. ______(Attorney Docket No. 20468-000310), entitled“Cluster Tool Systems and Methods for In Fab Wafer Processing,” filedcontemporaneously herewith, the complete disclosure of which isincorporated herein by reference.

[0083] The invention has now been described in detail for purposes ofclarity and understanding. However, it will be appreciated that certainchanges and modifications may be practiced within the scope of theappended claims. For example, the modules may have different layouts,dimensions and footprints than as described above. Additionally,transfer devices that have been described as traveling or fixed, mayalso be fixed or traveling, respectively.

What is claimed is:
 1. A method of processing a wafer, comprising:providing a wafer having initial thickness variations between twosurfaces of said wafer; processing said wafer through a first module,said first module comprising apparatus for performing a grindingprocess, a clean process and a metrology process, and said processingtherethrough includes said grinding process, said clean process and saidmetrology process; defining an edge profile on said wafer; andprocessing said wafer through a second module, said second modulecomprising apparatus for performing a double side polish (DSP) process,a clean process and a metrology process, and said processingtherethrough includes said DSP process, said clean process and saidmetrology process.
 2. The method of claim 1 wherein said first moduleprocessing further comprises an etch process, said etch process reducingsaid wafer thickness by less than about ten (10) microns.
 3. The methodof claim 1 wherein said first module processing precedes said definingsaid edge profile.
 4. The method of claim 1 wherein said first andsecond modules each comprise a cluster tool defining a clean roomenvironment.
 5. The method of claim 1 wherein said first modulemetrology process is simultaneous with said grinding process.
 6. Themethod of claim 5 wherein said first module metrology process produces ametrology profile for said wafer, said processing through said firstmodule further comprising modifying said grinding process in response tosaid metrology profile.
 7. The method of claim 1 wherein said firstmodule metrology process is after said grinding process.
 8. The methodof claim 1 further comprising polishing said edge of said wafer aftersaid defining said edge profile.
 9. The method of claim 1 furthercomprising processing said wafer through a third module, said thirdmodule comprising apparatus for performing a finish polish process, aclean process and a metrology process, and wherein said processingthrough said third module comprises said finish polishing process, saidclean process and said metrology process.
 10. The method of claim 9further comprising, after completion of said processing through saidthird module, providing said wafer directly to a process chamber forfabrication of a semiconductor device.
 11. The method of claim 9 furthercomprising, in order after completion of said processing through saidthird module, cleaning said wafer, inspecting said wafer, packaging saidwafer, and delivering said wafer to a wafer process facility forsubsequent fabrication of a semiconductor device.
 12. The method ofclaim 1 wherein said wafer has a total thickness variation (TTV) betweensaid two surfaces of less than about 0.3 microns after said processingthrough said second module.
 13. The method of claim 1 wherein said waferhas a SFQR of less than 0.12 microns after said processing through saidsecond module.
 14. The method of claim 1 further comprising processingsaid wafer through at least a portion of said first module prior toprocessing a second wafer through said first module.
 15. The method ofclaim 1 further comprising laser marking said wafer prior to saiddefining said edge profile.
 16. The method of claim 1 further comprisingperforming a donor anneal process prior to said defining said edgeprofile.
 17. The method of claim 1 , further comprising processing saidwafer through a third module, said third module comprising apparatus forperforming said defining said edge profile, and an edge polishingprocess, said processing through said third module comprising saiddefining said edge profile and said polishing said wafer edge.
 18. Amethod of processing a wafer prior to device formation thereon, saidmethod comprising, in order: providing a wafer having first and secondsurfaces and a peripheral edge; grinding said first and second wafersurfaces; defining an edge profile of said wafer, and polishing saidperipheral edge; and polishing said first and second wafer surfaces. 19.A wafer processing system, comprising: a grinder for grinding first andsecond wafer surfaces; an etcher for etching said wafer; a cleaner forcleaning said wafer; and a metrology tester for testing a metrology ofsaid wafer; wherein said grinder, etcher, cleaner and metrology testerare contained within a first clean room environment.
 20. The waferprocessing system as in claim 19 further comprising a transfer mechanismadapted to transfer said wafer from said grinder to said etcher withinsaid first clean room environment.
 21. The wafer processing system as inclaim 20 wherein said transfer mechanism comprises a robot.
 22. Thewafer processing system as in claim 19 further comprising a second cleanroom environment, said second clean room environment comprising: an edgegrinder for defining an edge profile of said wafer; and an edge polisherfor polishing said wafer edge.
 23. The wafer processing system as inclaim 19 further comprising a third clean room environment, said thirdclean room environment comprising: a polisher for polishing said wafer;a cleaner for cleaning said wafer; and a metrology tester for testingsaid wafer metrology.
 24. The wafer processing system as in claim 19further comprising a fourth clean room environment, said fourth cleanroom environment comprising: a finish polisher for polishing said wafer;a cleaner for cleaning said wafer; and a metrology tester for testingsaid wafer metrology.
 25. A wafer processing system, comprising: meansfor grinding said wafer; means for cleaning said wafer; means fortesting a wafer metrology; wherein said means for grinding, cleaning andtesting are contained within a single clean room environment; and meansfor transferring said wafer between said means for grinding and saidmeans for cleaning, within said clean room environment.